1. Field of the Invention
The present invention relates to a signal input/output device for a computer, a communication apparatus, or the like and more particularly, to a data transmission system which adjusts a variation in propagation delay time (data skew) between data bits and a clock skew to realize high speed data transmission in data transfer between synchronous parallel input/output device.
2. Description of the Related Art
In fields relating to data transfer between LSI's of a computer or to high speed data transmission between computers, there has been a widely employed synchronous data transmission system in which input/output devices provided at signal send/receive sides are controlled by clocks having an identical frequency. Accordingly, in order to increase the performance of a computer or computer system, it is important to increase the synchronous data transmission rate.
For the purpose of increasing the data transmission rate of synchronous data transmission to be carried out through a plurality of conductors such as a cable or a bus, it is necessary to perform data transmission with a cycle shorter than the data propagation delay time between the input/output devices. However, even when the data transmission system is a wave pipelined transfer type, it is difficult to sufficiently increase the transmission rate between parallel input/output devices having a data width of a plurality of bits. This is because the presence of variations (skews) in the data and clock propagation delay time causes reduction of the transmission cycle to be limited.
For the purpose of realizing the reduction of the transmission cycle, a technique for adjusting the data and clock skews is required.
A data skew adjustment technique is disclosed in JP-A-5-75594, a paper entitled "ATM 156 Mb/s Serial Interface CMOS-LSI" reported in Proceedings of the 1992 Spring Meeting of the Institute of Electronics, Information and Communication Engineers, B-445, JP-A-1-320841, JP-A-1-296734 and JP-A-2-7736.
Meanwhile, for the purpose of reducing the clock skew, it is generally necessary to wire clock distribution paths from a reference clock generator to respective input/output devices with an accurately equal length through complex calculation or on a simulation basis. JP-A-6-12140 discloses a technique for eliminating the need for such equal-length wiring of the block distribution paths.
A data skew adjustment technique such as the one mentioned above is roughly divided into two methods which follow. That is, in the first method, a multi-phase clock which is synchronized with a reference clock is generated in a receiver and received data is synchronized with use of the clock for latching the received data at the optimum timing. In the second method, a variable delay circuit is provided for every bit of data received in a receiver to control a delay for each bit such that all of the bits can be synchronized, thereby reducing a data skew.
However, the first method is defective in that it is difficult to realize an accurate phase relationship in the multi-phase clock. For example, when it is desired to use a 4-phase clock to synchronize received data having a high transmission frequency of 100 MHz or a transmission cycle of 10 nanoseconds, clocks having phases shifted accurately by 2.5 nanoseconds are required. In the case of fixed delay elements, since the propagation delay times negligibly among manufactured elements, it is difficult to generate such a 4-phase clock. In the case of phase-locked loop (PLL), since the PLL requires generation of a high frequency signal, this causes the operation of an analog controller to be unstable, leading to the fact that the noise influence by a digital signal may become a bottleneck in the system design.
The second method is defective in that the circuit scale is made large. For finely controlling each bit in the data received with respect to delay thereof, this inevitably involves an increase in the number of delay stages in the variable delay circuit and correspondingly also involves an increase in the scale of the control circuit, which makes it difficult to apply this method to a data transmission system so as to have a data width of several bytes.
The first and second methods have a common defect, that is, these methods do not take application to bus type transmission systems into consideration. Any of the techniques disclosed is directed to only 1:1 data transmission between a single receiver and a single transmitter, but in the case of a bus type transmission system, it becomes necessary for a single receiver to be able to execute data transfer with a plurality of transmitters.
Further, in a 1:1 transmitter/receiver system for performing data transmission over more than several meters, its data skew is relatively large and it is impossible in the prior art to perform data transmission with a cycle shorter than the magnitude of the data skew, which also leads to hinderance of realization of a higher transmission rate.
The prior art clock skew adjustment technique has the following defect. The method of reducing a clock skew by realizing clock distribution paths connecting a reference clock generator and respective input/output devices by using equal length wiring is limited by its structural aspect, in addition to the fact that it requires a lot of troublesome labor and time. This is because the propagation delay time of clock distribution paths actually manufactured is susceptible to manufacturing fluctuation and external electromagnetic waves and thus it is impossible to remove the clock skew as the designer expects at the time of its design.
In the technique disclosed in the above JP-A-6-12140, each of the input/output devices has a local clock generator operated in synchronism with the respective input/output devices and the clock phase of the local clock generator is adjusted so that all of the input/output devices are operated in synchronism with clocks having the same phase.
However, even if it became possible to remarkably reduce the clock skew with use of this technique, it is difficult to increase the data transmission rate of a wave pipeline type data transmission system. This is because, even if the clock skew is so small, it is not clear in the wave pipeline type system to determine which phase that data arrived with. For this reason, for the purpose of realizing the wave pipeline type system, there is employed, in many cases, a source synchronization system in which a transmitter sends a clock simultaneously with its transmission data. In a source synchronization type receiver, however, a means becomes necessary for once latching received data in synchronism with the clock of the source (transmitter) and then for again synchronizing it with the clock of the receiver, which disadvantageously results in that a time necessary between the transmission and reception of the data increase by an amount corresponding to the synchronizing means.